This invention relates to the fabrication of circuit packages, and in particular to a method of bonding solder preforms to electronic components and/or to supporting substrates.
The packaging of silicon integrated circuits by the use of hermetically sealed chip carriers is the subject of increasing interest in the industry. Typically, the circuit chip is bonded to one surface of the chip carrier, which is in turn bonded to a supporting substrate which can be a printed wiring board or a ceramic including a thick film or thin film circuit. A convenient method of bonding is by soldering together corresponding contact members on the carrier and substrate. Solder can be applied by dipping or printing. However, reliable connections usually require a precise solder volume per connection which is not easily obtainable by such methods. In addition, a large gap distance between the carrier and substrate is usually required to permit cleaning and encapsulation of the area of the substrate under the chip.
It has therefore been proposed to bond the carrier to the substrate, which include first and second sets of contact pads respectively, by bonding massive solder spheres to one set of pads, bringing the other set of contact pads into contact with the spheres and then bonding the pads together while maintaining a gap distance of at least 10 mils (see, U.S. Patent application of P. M. Hall et al., Ser. No. 107,327, filed on an even date herewith and assigned to the same assignee, which application is incorporated by reference herein). In accordance with one embodiment of that method, the spheres are first bonded to the carrier by fluxing the carrier, applying the spheres, reflowing the solder to form the bond, and then removing the flux. The procedure of fluxing, reflowing and cleaning is then repeated when the bumped carrier is bonded to the supporting substrate.
While the process described above is adequate for most purposes, it does result in a relatively low output and therefore would not appear to be optimum for high volume production. In addition, application and removal of flux provide additional cost to fabrication of a package. A further problem with a reflow process is that solder will flow into the castellations (grooves) of the carrier and therefore make probe testing of the carrier difficult.
It will also be appreciated that there are many other types of packaging which require a precise amount of solder for bonding, for example, bonding ceramic chip capacitors and silicon integrated circuit chips to hybrid integrated circuit substrates. In the latter case, for example, it may be desirable to apply solder preforms to a leadless chip, a beam lead contact, or the metal tape carrier used in the chip-and-tape technology. There are also packages which utilize thin film circuits bonded to a ceramic thin film circuit "mother" board.
It is therefore an object of the invention in the fabrication of circuit packages to provide a method of bonding an electronic component to a supporting substrate which permits high volume production while placing a precise solder volume at each bonding site.